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ltc3605a 1 3605af pv in rt ltc3605a clkout clkin pgood run intv cc boost sw fb sv in 2.2f v in 47f 2 3605a ta01a v out 3.3v 0.1f 220pf 11.5k 2.55k 16k 162k 1h 22f 2 v in 4v to 20v ith v on pgnd typical application features applications description 20v, 5a synchronous step-down regulator the ltc ? 3605a is a high effciency, monolithic synchro - nous buck regulator using a phase lockable controlled on-time constant frequency, current mode architecture. polyphase operation allows multiple ltc3605a regula - tors to run out of phase while using minimal input and output capacitance. the operating supply voltage range is from 20v down to 4v, making it suitable for dual, triple or quadruple lithium-ion battery inputs as well as point of load power supply applications from a 12v or 5v rail. the operating frequency is programmable from 800khz to 4mhz with an external resistor. the high frequency capabil - ity allows the use of small surface mount inductors. for switching noise sensitive applications, it can be externally synchronized from 800khz to 4mhz. the phmode pin allows user control of the phase of the outgoing clock signal. the unique constant frequency/controlled on-time architecture is ideal for high step-down ratio applications that are operating at high frequency while demanding fast transient response. two internal phase-lock loops synchronize the internal oscillator to the external clock and also servos the regulator on-time to lock on to either the internal clock or the external clock if its present. high effciency 1mhz, 5a step-down regulator n high effciency: up to 96% n 5a output current n 4v to 20v v in range n integrated power n-channel mosfets (70m top and 35m bottom) n adjustable frequency 800khz to 4mhz n polyphase ? operation (up to 12 phases) n output tracking n 0.6v 1% reference accuracy n current mode operation for excellent line and load transient response n shutdown mode draws less than 15a supply current n ltc3605: 15v absolute maximum v in n ltc3605a: 22v absolute maximum v in n the ltc3605a is pin compatible with the ltc3605 n available in 24-pin (4mm 4mm) qfn package n point of load power supply n portable instruments n distributed power systems n battery-powered equipment effciency and power loss l , lt, ltc, ltm, polyphase, opti-loop, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. load current (a) 0.01 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 3605a ta01b 30 20 10 0 90 100 1 0.1 0.01 10 v out = 3.3v v in = 8v v in = 12v v in = 20v
ltc3605a 2 3605af pin configuration absolute maximum ratings pv in , sv in , sw voltage .............................. C0.3v to 22v sw transient voltage ................................. C2v to 24.5v boost voltage .......................... C0.3v to pv in + intv cc run voltage ............................................. C0.3v to sv in v on voltage ............................................... C0.3v to sv in intv cc voltage .......................................... C0.3v to 3.6v ith, rt, clkout, pgood voltage ......... C0.3v to intv cc clkin, phmode, mode voltage .......... C0.3v to intv cc track/ss, fb voltage .......................... C0.3v to intv cc operating junction temperature range (note 2) .................................................. C40c to 125c storage temperature range ................... C65c to 125c (note 1) 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 rt phmode mode fb track/ss ith pv in pv in sw sw sw sw clkin clkout sgnd intv cc boost sv in run pgood v on pgnd sw sw 25 pgnd t jmax = 125c, ja = 37c/w exposed pad (pin 25) is pgnd, must be soldered to pcb order information electrical characteristics symbol parameter conditions min typ max units sv in sv in supply range 4 20 v pv in v in power supply range 1.2 20 v i q input dc supply current active shutdown (note 3) mode = 0, r t = 162k v in =12v, run = 0 1.5 11 5 40 ma a v fb feedback reference voltage ith =1.2v (note 4) l 0.594 0.600 0.606 v dv fb(line) feedback voltage line regulation v in = 4v to 20v, ith = 1.2v l 0.001 0.03 %/v dv fb(load) feedback voltage load regulation l 0.1 0.3 % i fb feedback pin input current 30 na g m (ea) error amplifer transconductance ith = 1.2v 1.15 1.35 1.6 ms t on(min) minimum on-time 40 ns t off(min) minimum off-time 70 ns the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j t a = 25c. (note 2) lead free finish tape and reel part marking* package description temperature range ltc3605aeuf#pbf ltc3605aeuf#trpbf 3605a 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3605aiuf#pbf ltc3605aiuf#trpbf 3605a 24-lead (4mm 4mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc3605a 3 3605af electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3605a is tested under pulsed load conditions such that t j t a . the ltc3605ae (e-grade) is guaranteed to meet specifcations from 0c to 85c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3605ai (i-grade) is guaranteed over the full C40c to 125c operating temperature range. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d ? ja c/w) where ja is the package thermal impedance. note that the maximum ambient temperature is determined by specifc operating conditions in conjunction with board layout, the rated thermal package thermal resistance and other environmental factors. the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j t a = 25c. (note 2) note 3: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 4: the ltc3605a is tested in a feedback loop that adjusts v fb to achieve a specifed error amplifer output voltage (ith). note 5: t j is calculated from the ambient temperature t a and power dissipation as follows: t j = t a + p d ? (37c/w). see thermal considerations section. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active continuous operation above the specifed maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units i lim positive inductor valley current limit v fb = 0.57v 5 6 7.5 a r top top power nmos on-resistance intv cc = 3.3v 70 150 mw r bottom bottom power nmos on-resistance intv cc = 3.3v 35 60 mw v uvlo intv cc undervoltage lockout threshold intv cc falling intv cc hysteresis (rising) 2.4 2.6 0.25 2.8 v v v run run threshold 2 (i q = 2ma) run threshold 1 (i q = 400a) run rising run rising 1.2 0.45 1.25 0.6 1.3 0.75 v v v intvcc internal v cc voltage 4v < v in < 20v 3.2 3.3 3.4 v dv intvcc intv cc load regulation i load = 0ma to 20ma 0.5 % ov output overvoltage pgood upper threshold v fb rising 7 10 13 % uv output undervoltage pgood lower threshold v fb falling C13 C10 C7 % dv fb(hys) pgood hysteresis v fb returning 1.5 % r pgood pgood pull-down resistance 1ma load 12 25 w i pgood pgood leakage 0.54v < v fb < 0.66v 2 a i track/ss track pull-up current 2.5 4 a f osc oscillator frequency r t = 162k l 0.85 1 1.2 mhz clkin clkin threshold clkin v il clkin v ih 1 0.3 v v v vin_ov v in overvoltage lockout threshold v in rising v in falling 23 21 23.5 21.5 24 22 v v
ltc3605a 4 3605af typical performance characteristics quiescent current vs v in effciency vs load current shutdown current vs v in r ds(on) vs temperature load regulation load step (external ith compensation) output tracking i intvcc current vs frequency temperature (c) ?45 0 r ds(on) (m) 20 40 60 80 5 55 3605a g04 100 120 ?20 30 80 105 130 top fet bottom fet i out (a) 0 normalized (%) 0.5 1.0 1.5 3 5 3605a g05 0 ?0.5 1 2 4 6 7 ?1.0 ?1.5 v in = 12v v out = 1.2v f = 1mhz mode = intv cc internal ith compensation (ith = 3.3v) external ith compensation load step (internal ith compensation) frequency (mhz) 0 0 i intvcc (ma) 5 15 20 25 1 2 2.5 4.5 3605a g03 10 0.5 1.5 3 3.5 4 mode = 3.3v no load v in = 12v v out = 1.2v 500s/div 3605a g08 v track v fb t a = 25c unless otherwise specifed. input voltage (v) 0 quiescent current (ma) 1.0 1.5 16 3605a g01 0.5 0 4 8 12 20 2.0 input voltage (v) 0 shutdown current (a) 10 15 16 3605a g02 5 0 4 8 12 20 20 v in = 12v v out = 1.2v i load = 0.4a v out 100mv/div ac-coupled i l 5a/div i load 5a/div 20s/div 3605a g06 v in = 12v v out = 1.2v i load = 0.4a ith = 3.3v v out 100mv/div ac-coupled i l 5a/div i load 5a/div 20s/div 3605a g07 load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3605a g18 30 20 10 0 90 100 v in = 12v f sw = 1mhz v out = 3.3v v out = 2.5v v out = 1.8v
ltc3605a 5 3605af switching frequency vs r t switch leakage vs v in effciency vs v in frequency vs v on voltage current limit foldback intv cc load regulation run pin threshold vs temperature dcm operation r t (k) 0 0 frequency (mhz) 0.5 1.5 2.0 2.5 300 350 400 450 4.5 3605a g09 1.0 50 100 150 200 250 500 3.0 3.5 4.0 v fb (v) 0 normalized maximum output current (%) 80 100 120 0.3 0.5 3605a g13 60 40 0.1 0.2 0.4 0.6 0.7 20 0 intv cc output current (ma) 0 normalized intv cc (%) 93 99 100 101 40 80 100 3605a g14 91 97 95 92 98 90 96 94 20 60 120 140 t a = 25c temperature (c) ?40 run threshold (v) 1.20 1.25 1.30 35 85 3605a g15 1.15 1.10 ?15 10 60 110 1.05 1.00 ccm operation typical performance characteristics t a = 25c unless otherwise specifed. v in (v) 0 0 switch leakage (na) 50 150 200 250 350 2 10 14 3605a g10 100 300 8 18 20 4 6 12 16 v in (v) 0 efficiency (%) 86 88 90 15 25 3505a g11 84 82 80 5 10 20 92 94 i load = 1a v out = 3.3v i load = 5a 96 v in = 20v v out = 2.5v mode = 0v i out = 0a l1 = 0.5h clkout 2v/div v sw 5v/div i l 2a/div 400ns/div 3605a g16 v in = 20v v out = 2.5v mode = 3.3v i out = 0a l1 = 0.5h clkout 2v/div v sw 5v/div i l 2a/div 400ns/div 3605a g17 v on (v) 0 0 frequency (mhz) 0.5 1.5 2.0 2.5 4 8 10 18 3605a g12 1.0 2 6 12 14 16 3.0 v in = 20v r t = 162k
ltc3605a 6 3605af pin functions rt (pin 1): oscillator frequency programming pin. con - nect an external resistor (between 200k to 40k) from rt to sgnd to program the frequency from 800khz to 4mhz. since the synchronization range is 30% of set frequency, be sure that the set frequency is within this percentage range of the external clock to ensure frequency lock. phmode (pin 2): control input to phase selector. deter - mines the phase relationship between internal oscillator and clkout. tie it to intv cc for 2-phase operation, tie it to sgnd for 3-phase operation, and tie it to intv cc /2 for 4-phase operation. mode (pin 3): operation mode select. tie this pin to intv cc to force continuous synchronous operation at all output loads. tying it to sgnd enables discontinuous mode operation at light loads. tying this pin to intv cc /2 shuts off the internal clock during discontinuous intervals. fb (pin 4): output feedback voltage. input to the error amplifer that compares the feedback voltage to the internal 0.6v reference voltage. this pin is normally connected to a resistive divider from the output voltage. track/ss (pin 5): output tracking and soft-start pin. allows the user to control the rise time of the output volt - age. putting a voltage below 0.6v on this pin bypasses the internal reference input to the error amplifer, instead it servos the fb pin to the track voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifer. theres an internal 2a pull-up current from intv cc on this pin, so putting a capacitor here provides soft-start function. ith (pin 6): error amplifer output and switching regu - lator compensation point. the current comparators trip threshold is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v. tying this pin to intv cc activates internal compensation and output voltage po - sitioning, raising v out to 1.5% higher than the nominal value at i out = 0 and 1.5% lower at i out = 5a. run (pin 7): run control input. enables chip operation by tying run above 1.2v. tying it below 1.1v shuts down the part. pgood (pin 8): output power good with open-drain logic. pgood is pulled to ground when the voltage on the fb pin is not within 10% of the internal 0.6v reference. v on (pin 9): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output volt - age makes the on-time proportional to v out and keeps the switching frequency constant at different v out . however, when v on is <0.6v or >6v, then switching frequency will no longer remain constant. pgnd (pin 10, exposed pad pin 25): power ground. return path of internal power mosfets. connect this pin to the negative terminals of the input capacitor and output capacitor. the exposed pad must be soldered to the pcb ground for electrical contact and rated thermal performance. sw (pins 11 to 16): switch node connection to external inductor. voltage swing of sw is from a diode voltage drop below ground to pv in . pv in (pins 17, 18): power v in . input voltage to the on- chip power mosfets. sv in (pin 19): signal v in . filtered input voltage to the on-chip 3.3v regulator. connect a (1 to 10) resistor between sv in and pv in and bypass to gnd with a 0.1f capacitor. boost (pin 20): boosted floating driver supply for inter - nal top power mosfet. the (+) terminal of the bootstrap capacitor connects here. this pin swings from a diode voltage drop below intv cc up to pv in + intv cc . intv cc (pin 21): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 1f low esr ceramic capacitor. sgnd (pin 22): signal ground connection. clkout (pin 23): output clock signal for polyphase operation. the phase of clkout with respect to clkin is determined by the state of the phmode pin. clkouts peak-to-peak amplitude is intv cc to gnd. clkin (pin 24): external synchronization input to phase detector. this pin is internally terminated to sgnd with 20k. the phase-locked loop will force the top power nmoss turn on signal to be synchronized with the rising edge of the clkin signal.
ltc3605a 7 3605af block diagram ? ++ ? + ? + 19 sv in mode 3pf 100k 35pf 20k q6 3.3a run switch logic and anti- shoot through bg ov on 1 180k q1 q2 0.6v 1.2v run ea ss q4 track/ss c ss 5 7 3605a bd sgnd r2 r1 22 4 run 10, 25 pgnd pgood fb sw tg c b pv in 17-18 c in boost 11?16 sense + sense ? 20 1 ? + ? + ov 0.66v ? + 0.3v foldback x 4 + 0.6 foldback disabled at start-up uv 0.54v c vcc 6v 0.6v v out int vcc v out m2 m1 l1 c out intv cc ith r c c c1 6 c in2 ? + ? + 2a 0a to 10a ?3.3a to 6.7a d b i thb i cmp i rev 8 3.3v reg i on pll-sync (30%) osc pll-sync (30%) 12 x osc 35pf 100k 3pf 9 3 21 r 0.6v ref s q 2 phmode 24 23 i on ost clkout clkin rt r t v on x = v in intv cc t on = (0.64pf) v von i ion 1
ltc3605a 8 3605af operation main control loop the ltc3605a is a current mode monolithic step-down regulator. in normal operation, the internal top power mosfet is turned on for a fxed interval determined by a one-shot timer, ost. when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator, i cmp , trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage drop across the bottom power mosfet s vds. the voltage on the ith pin sets the com - parator threshold corresponding to the inductor valley current. the error amplifer, ea, adjusts this ith voltage by comparing the feedback signal, v fb , from the output voltage with that of an internal 0.6v reference. if the load current increases, it causes a drop in the feedback volt - age relative to the internal reference. the ith voltage then rises until the average inductor current matches that of the load current. at low load current, the inductor current can drop to zero and become negative. this is detected by current reversal comparator, i rev , which then shuts off the bottom power mosfet, resulting in discontinuous operation. both power mosfets will remain off with the output capacitor supplying the load current until the ith voltage rises above the zero current level (0.6v) to initiate another cycle. discontinu - ous mode operation is disabled by tying the mode pin to intv cc , which forces continuous synchronous operation regardless of output load. the operating frequency is determined by the value of the r t resistor, which programs the current for the internal oscillator. an internal phase-lock loop servos the oscillator frequency to an external clock signal if one is present on the clkin pin. another internal phase-lock loop servos the switching regulator on-time to track the internal oscillator to force constant switching frequency. overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback volt - age, v fb , exits a 10% window around the regulation point. continuous operation is forced during ov and uv condition except during start-up when the track pin is ramping up to 0.6v. foldback current limiting is provided if the output is shorted to ground. as v fb drops to zero, the maximum sense voltage allowed across the bottom power mosfet is lowered to approximately 40% of the original value to reduce the inductor valley current. pulling the run pin to ground forces the ltc3605a into its shutdown state, turning off both power mosfets and most of its internal control circuitry. bringing the run pin above 0.6v turns on the internal reference only, while still keeping the power mosfets off. further increasing the run voltage above 1.25v turns on the entire chip. intv cc regulator an internal low dropout (ldo) regulator produces the 3.3v supply that powers the drivers and the internal bias circuitry. the intv cc can supply up to 100ma rms and must be bypassed to ground with a minimum of 1f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the power mosfet gate drivers. applications with high input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the ldo. connect- ing a load to the intv cc pin is not recommended since it will further push the ldo into its rms current rating while increasing power dissipation and die temperature. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltc3605a constantly monitors the v in pin for an overvoltage condition. when v in rises above 23.5v, the regulator suspends operation by shutting off both power mosfets. once v in drops below 21.5v, the regulator immediately resumes normal operation. the regulator does not execute its soft-start function when exiting an overvoltage condition.
ltc3605a 9 3605af output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.6v ? (1 + r2/r1) the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 1. output power good when the ltc3605as output voltage is within the 10% window of the regulation point, which is refected back as a v fb voltage in the range of 0.54v to 0.66v, the output voltage is good and the pgood pin is pulled high with an external resistor. otherwise, an internal open-drain pull- down device (12) will pull the pgood pin low. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3605as pgood falling edge includes a blanking delay of approximately 52 switching cycles. multiphase operation for output loads that demand more than 5a of current, multiple ltc3605as can be cascaded to run out of phase to provide more output current. the clkin pin allows the ltc3605a to synchronize to an external clock (30% of frequency programmed by rt) and the internal phase- locked-loop allows the ltc3605a to lock onto clkins phase as well. the clkout signal can be connected to the clkin pin of the following ltc3605a stage to line up both the frequency and the phase of the entire system. tying the phmode pin to intv cc , sgnd or intv cc /2 generates a phase difference (between clkin and clkout) of 180 degrees, 120 degrees, or 90 degrees respectively, which corresponds to 2-phase, 3-phase or 4-phase operation. a total of 12 phases can be cascaded to run simultaneously out of phase with respect to each other by programming the phmode pin of each ltc3605a to different levels. internal/external ith compensation during single phase operation, the user can simplify the loop compensation by tying the i th pin to intv cc to enable internal compensation. this connects an internal 30k resistor in series with a 40pf capacitor to the output of the error amplifer (internal ith compensation point) while also activating output voltage positioning such that the output voltage will be 1.5% above regulation at no load and 1.5% below regulation at full load. this is a trade-off for simplicity instead of opti-loop ? optimiza- tion, where ith components are external and are selected to optimize the loop transient response with minimum output capacitance. operation figure 1. setting the output voltage programming switching frequency connecting a resistor from the rt pin to sgnd programs the switching frequency from 800khz to 4mhz according to the following formula: frequency (hz) = 1.6e11 r t ( w ) the internal pll has a synchronization range of 30% around its programmed frequency. therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the rt pro - grammed frequency. output voltage tracking and soft-start the ltc3605a allows the user to program its output voltage ramp rate by means of the track/ss pin. an internal 2a pulls up the track/ss pin to intv cc . putting an external capacitor on track/ss enables soft starting the output to prevent current surge on the input supply. for output tracking applications, track/ss can be externally driven by another voltage source. from 0v to 0.6v, the track/ss voltage will override the internal 0.6v reference input to the error amplifer, thus regulating the feedback voltage to that of track/ss pins. during this start-up time, the ltc3605a will operate in discontinuous mode. when track/ss is above 0.6v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. fb r2 v out c ff r1 3605a f01 ltc3605a sgnd
ltc3605a 10 3605af minimum off-time and minimum on-time considerations the minimum off-time, t off(min) , is the smallest amount of time that the ltc3605a is capable of turning on the bot - tom power mosfet, tripping the current comparator and turning the power mosfet back off. this time is generally about 70ns. the minimum off-time limit imposes a maxi - mum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out ? t on + t off(min) t on conversely, the minimum on-time is the smallest dura - tion of time in which the top power mosfet can be in its on state. this time is typically 40ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc min gtu on(min) where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regula- tion, but the switching frequency will decrease from its programmed value. this is an acceptable result in many applications, so this constraint may not be of critical importance in most cases. high switching frequencies may be used in the design without any fear of severe consequences. as the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the size of the application circuit. c in and c out selection the input capacitance, c in , is needed to flter the trapezoi - dal wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum r ms current should be used. the maximum r ms current is given by: i rms ? i out(max) v out v in v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms ? i out /2. this simple worst-case condition is com - monly used for design because even signifcant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, suffcient bulk input capacitance is needed to minimize transient effects during output load changes. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, dv out , is determined by: d v out < d i l 1 8 ? f ? c out + esr ? ? ? ? ? ? the output ripple is highest at maximum input voltage since di l increases with input voltage. multiple capaci- tors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors are very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signifcantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. their relatively low value of bulk capacitance may require multiples in parallel. operation
ltc3605a 11 3605af using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage charac - teristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the frst cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 3 times the linear drop of the frst cycle. thus, a good place to start with the output capacitor value is approximately: c out 2.5 d i out f o ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 22f ceramic capacitor is usually enough for these conditions. place this input capacitor as close to the pv in pins as possible. operation inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: d i l = v out f ? l 1? v out v in(max) ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest effciency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, effciency and operating frequency. a reasonable starting point is to choose a ripple current that is about 50% of i out(max) . this is especially impor - tant at low v out operation where v out is 1.8v or below. care must be given to choose an inductance value that will generate a big enough current ripple (40% to 50%) so that the chips valley current comparator has enough signal-to-noise ratio to force constant switching frequency. meanwhile, also note that the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specifed maximum, the inductance should be chosen according to: l = v out f ? d i l(max) ? 1? v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fxed inductor value, but is very dependent on the inductance selected. as the inductance or frequency in- creases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that
ltc3605a 12 3605af inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! operation table 1. inductor selection table inductance dcr max current dimensions height vishay ihlp-2525cz-01 series 0.33h 4.1mw 18a 6.7mm 7mm 3mm 0.47h 6.5mw 13.5a 0.68h 9.4mw 11a 0.82h 11.8mw 10a 1.0h 14.2mw 9a vishay ihlp-1616bz-11 series 0.22h 4.1mw 12a 4.3mm 4.7mm 2.0mm 0.47h 15mw 7a toko fdv0620 series 0.20h 4.5mw 12.4a 7mm 7.7mm 2.0mm 0.47h 8.3mw 9a 1h 18.3mw 5.7a nec/tokin mlc0730l series 0.47h 4.5mw 16.6a 6.9mm 7.7mm 3.0mm 0.75h 7.5mw 12.2a 1h 9mw 10.6a cooper hcp0703 series 0.22h 2.8mw 23a 7mm 7.3mm 3.0mm 0.47h 4.2mw 17a 0.68h 5.5mw 15a 0.82h 8mw 13a 1h 10mw 11a 1.5h 14mw 9a tdk rlf7030 series 1h 8.8mw 6.4a 6.9mm 7.3mm 3.2mm 1.5h 9.6mw 6.1a 2.2h 12mw 5.4a wurth electronik we-hc 744312 series 0.25h 2.5mw 18a 7mm 7.7mm 3.8mm 0.47h 3.4mw 16a 0.72h 7.5mw 12a 1h 9.5mw 11a 1.5h 10.5mw 9a different core materials and shapes will change the size/cur - rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated feld/emi requirements. new designs for surface mount inductors are available from toko, vishay, nec/tokin, cooper, tdk and wurth electronik. refer to table 1 for more details. checking transient response the opti-loop compensation allows the transient re - sponse to be optimized for a wide range of loads and output capacitors. the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac-fltered closed-loop response test point. the dc step, rise time and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the ith external components shown in the circuit on the frst page of this data sheet provides an adequate starting point for most applications. the series r-c flter sets the dominant pole zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values deter - mine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to d i load ? esr, where esr is the effective series resistance of c out . di load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its
ltc3605a 13 3605af steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the band - width of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with the r and the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , can be added to improve the high frequency response, as shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this prob - lem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifcally for this purpose and usually in- corporates current limiting, short-circuit protection and soft-starting. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: % effciency = 100%C(l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ltc3605a circuits: 1) i 2 r losses, 2) switching and biasing losses, 3) other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current fows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1-dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the intv cc current is the sum of the power mosfet driver and control currents. the power mosfet driver current results from switching the gate capacitance of the power mosfets. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. since intv cc is a low dropout regulator output powered by v in , its power loss equals: p ldo = v in ? i intvcc refer to the i intvcc vs frequency curve in the typical performance characterics for typical intv cc current at various frequencies. 3. other hidden losses such as transition loss and cop - per trace and internal load resistances can account for additional effciency degradations in the overall power operation
ltc3605a 14 3605af operation system. it is very important to include these system level losses in the design of a system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the ltc3605a internal power devices switch quickly enough that these losses are not signif - cant compared to other sources. other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3605a does not dis - sipate much heat due to its high effciency and low thermal resistance of its exposed-back qfn package. however, in applications where the ltc3605a is running at high ambi - ent temperature, high v in , high switching frequency and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 160c, both power switches will be turned off until the temperature drops about 15c cooler. to avoid the ltc3605a from exceeding the maximum junc - tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja as an example, consider the case when the ltc3605a is used in applications where v in = 12v, i out = 5a, f = 1mhz, v out = 1.8v. the equivalent power mosfet resistance r sw is: r sw = r ds(on) top s v out v in + r ds(on) bot 1? v out v in ? ? ? ? ? ? = 70m w 1.8 12 + 35m w 10.2 12 = 40.25m w the v in current during 1mhz force continuous operation with no load is about 11ma, which includes switching and internal biasing current loss, transition loss, inductor core loss and other losses in the application. therefore, the total power dissipated by the part is: p d = i out 2 ? r sw + v in ? i vin (no load) = 25a 2 ? 40.25m + 12v ? 11ma = 1.14w the qfn 4mm 4mm package junction-to-ambient thermal resistance, ja , is around 37c/w. therefore, the junction temperature of the regulator operating in a 25c ambient temperature is approximately: t j = 1.14w ? 37c/w + 25c = 67c remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation assuming that r sw increased 15% at 67c yields a new junction temperature of 72c. if the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air fow. figure 2 is a temperature derating curve based on the dc1215 demo board. figure 2. load current vs ambient temperature junction temperature measurement the junction-to-ambient thermal resistance will vary de - pending on the size and amount of heat sinking copper on the pcb board where the part is mounted, as well as the amount of air fow on the device. one of the ways to ambient temperature (c) 20 0 load current (a) 1 2 3 4 6 40 60 80 100 3605a f02 120 140 5 v in = 12v v out = 3.3v f sw = 1mhz dc1215 demo board
ltc3605a 15 3605af operation measure the junction temperature directly is to use the internal junction diode on one of the pins (pgood) to measure its diode voltage change based on ambient temperature change. first remove any external passive component on the pgood pin, then pull out 100a from the pgood pin to turn on its internal junction diode and bias the pgood pin to a negative voltage. with no output current load, measure the pgood voltage at an ambient temperature of 25c, 75c and 125c to estab- lish a slope relationship between the delta voltage on pgood and delta ambient temperature. once this slope is established, then the junction temperature rise can be measured as a function of power loss in the package with corresponding output load current. keep in mind that doing so will violate absolute maximum voltage ratings on the pgood pin, however, with the limited current, no damage will result. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3605a (refer to figure 3). check the following in your layout: 1. do the capacitors c in connect to the power pv in and power pgnd as close as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. 2. are c out and l1 closely connected? the (C) plate of c out returns current to pgnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line termi- nated near sgnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace should be minimized. keep r1 and r2 close to the ic. 4. solder the exposed pad (pin 25) on the bottom of the package to the pgnd plane. connect this pgnd plane to other layers with thermal vias to help dissipate heat from the ltc3605a. 5. keep sensitive components away from the sw pin. the r t resistor, the compensation capacitor c c and c ith and all the resistors r1, r3 and r c , and the intv cc bypass capacitor, should be placed away from the sw trace and the inductor l1. also, the sw pin pad should be kept as small as possible. 6. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small- signal components returning to the sgnd pin which is then connected to the pgnd pin at the negative terminal of the output capacitor, c out . flood all unused areas on all layers with copper, which reduces the temperature rise of power components. these copper areas should be connected to pgnd. figure 3a. sample pcb layouttopside figure 3b. sample pcb layoutbottom side v in gnd v out c in l1 3605a f03a c out v in v out 3605a f03b gnd
ltc3605a 16 3605af typical applications 12v to 1.2v 1mhz buck regulator operation design example as a design example, consider using the ltc3605a in an application with the following specifcations: v in = 10.8v to 13.2v, v out = 1.8v, i out(max) = 5a, i out(min) = 500ma, f = 2mhz because effciency is important at both high and low load current, discontinuous mode operation will be utilized. first select from the characteristic curves the correct r t resistor value for 2mhz switching frequency. based on that r t should be 80.6k. then calculate the inductor value for about 50% ripple current at maximum v in : l = 1.8v 2mhz ? 2.5a ? ? ? ? ? ? 1? 1.8v 13.2v ? ? ? ? ? ? = 0.31h the nearest standard value inductor would be 0.33h. c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, two 47f ceramic capacitors will be used. c in should be sized for a maximum current rating of: i rms = 5a 1.8v 13.2v ? ? ? ? ? ? 13.2v 1.8v ? 1 ? ? ? ? ? ? 1/ 2 = 1.7a decoupling the pv in pins with two 22f ceramic capacitors is adequate for most applications. clkin rt 24 1 2 3 4 5 6 23 c1 2.2f c in 22f 2 0.1f v in 4v to 20v v out 1.2v 5a 0.1f c out 47f 2 47f 0.1f 10pf 330pf 22 21 d1 20 19 10 18 17 16 l1 0.68h 15 14 13 7 8 100k c1: avx 0805zd225mat2a c in : tdk c4532x5ric226m c out : tdk c3216x5roj476m d1: central semi cmdsh-3 l1: vishay ihlp-2525czerr68-m01 162k 12k 4.99k 4.99k 3605a ta02 9 10 11 12 sgnd pgnd phmode mode fb track/ss ith pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in pgood v on pgnd sw sw
ltc3605a 17 3605af typical applications 12v, 10a 2-phase single output regulator clkin rt 24 1 2 3 4 5 6 23 c1 2.2f c in1 22f 2 0.1f 100pf v in 4v to 20v v out 3.3v 10a 0.1f 0.1f c out1 47f 2 0.1f 10pf 470pf 22 21 d1 20 19 10 18 17 16 l1 1.5h 15 14 13 7 8 100k 162k 5.4k 10pf 470pf 5.4k 10k 2.21k 9 10 11 12 sgnd pgnd phmode mode fb track/ss i th pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in pgood v on pgnd sw sw clkin rt 24 1 2 3 4 5 6 23 c2 2.2f c in2 22f 2 0.1f c out2 47f 22 21 d2 20 19 10 18 17 16 l2 1.5h 15 14 13 7 8 162k 3605a ta03 9 10 11 12 sgnd pgnd phmode mode fb track/ss ith pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in pgood v on pgnd sw sw c1, c2: avx 0805zd225mat2a c in1 , c in2 : tdk c4532x5ric226m c out1 , c out2 : tdk c3216x5roj476m d1, d2: central semi cmdsh-3 l1, l2: vishay ihlp-2525czer1r5-m01 load current (a) 0.1 0 efficiency (%) 20 40 60 80 1 10 3605a ta03b 100 10 30 50 70 90 dcm ccm 12v, 10a, 2-phase effciency 12v, 10a, 2-phase load step 20s/div i l1 2a/div i l2 2a/div v out 100mv/div ac-coupled 3605a ta03c
ltc3605a 18 3605af typical applications dual output tracking application dual output tracking waveform clkin rt 24 1 2 3 4 5 6 23 c1 2.2f c in1 22f 2 0.1f v in1 4v to 20v v out1 1.8v 5a 0.1f c out1 47f 0.1f 10pf 100pf 22 21 d1 20 19 10 18 17 16 l1 0.33h 15 14 13 7 8 100k 162k 16.2k 7.5k 2.49k 4.99k 9 10 11 12 sgnd pgnd phmode mode fb track/ss ith pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in1 pgood v on pgnd sw sw clkin rt 24 1 2 3 4 5 6 23 c2 2.2f c in2 22f 2 0.1f v in2 4v to 20v v out2 1.2v 5a 0.1f c out2 47f 10pf 100pf 22 21 d2 20 19 10 18 17 16 l2 0.33h 15 14 13 7 8 100k 162k 16.2k 4.99k 4.99k 3605a ta04 9 10 11 12 sgnd pgnd phmode mode fb track/ss ith pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in2 pgood v on pgnd sw sw c1, c2: avx 0805zd225mat2a c in1 , c in2 : tdk c4532x5ric226m c out1 , c out2 : tdk c3216x5roj476m d1, d2: central semi cmdsh-3 l1, l2: vishay ihlp-2525czerr33-m01 v in = 12v v out1 = 1.8v, v out2 = 1.2v i out1 = 80ma, i out2 = 80ma 500s/div v out1 500mv/div v out2 500mv/div 3605a ta04b
ltc3605a 19 3605af information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b)
ltc3605a 20 3605af linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0512 ? printed in usa related parts part number description comments ltc3605 15v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 4v to 15v, v out(min) = 0.6v, i q = 2ma, i sd < 1a, 4mm 4mm qfn24 ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% effciency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 3mm qfn16, mse16 ltc3414/ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converters 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd < 1a, tssop20e ltc3415 7a (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 450a, i sd < 1a, 5mm 7mm qfn38 ltc3608 18v, 8a (i out ) 1mhz, synchronous step-down dc/dc converter 95% effciency, v in : 4v to 18v, v out(min) = 0.6v, i q = 900a, i sd < 15a, 7mm 8mm qfn52 ltc3610 24v, 12a (i out ), 1mhz, synchronous step-down dc/dc converter 95% effciency, v in : 4v to 24v, v out(min) = 0.6v, i q = 900a, i sd < 15a, 9mm 9mm qfn64 LTC3611 32v, 10a (i out ), 1mhz, synchronous step-down dc/dc converter 95% effciency, v in : 4v to 32v, v out(min) = 0.6v, i q = 900a, i sd < 15a, 9mm 9mm qfn64 typical application C3.6v negative converter clkin rt 24 1 d1 2 3 4 5 6 23 c1 2.2f c in 22f 2 0.1f v in 3v to 16v v out ?3.6v 2a 0.1f c out 47f 2 0.1f 47pf 470pf 22 21 20 19 10 18 17 16 l1 1h 15 14 13 7 8 100k 162k 16.2k 24.9k 4.99k 3605a ta05 9 10 11 12 phmode mode fb track/ss i th pv in pv in sw sw sw sw clkout sgnd ltc3605a intv cc boost sv in run sv in pgood v on pgnd sw sw C3.6v negative converter effciency C3.6v negative converter load current (a) 0.01 0 efficiency (%) 20 40 60 80 1 0.1 10 3605a ta05b 100 10 30 50 70 90 dcm ccm v in = 12v v out = ?3.6v i load = 2a 400ns/div sw i l 2a/div 3605a ta05c

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